Torna a Texas Instruments

Texas Instruments LMK04228 Ultra Low-Noise Clock Jitter Cleaners

Texas Instruments LMK04228 Ultra-Low-Noise Clock Jitter Cleaners offer high-performance and JEDEC JESD204B support. The device provides 14 clock outputs from PLL2 that can be configured to drive seven JESD204B converters or other logic devices using device and SYSREF clocks. SYSREF can be provided using both DC and AC coupling. Each of the 14 outputs can be individually configured as high-performance outputs for traditional clocking systems, not limited to JESD204B applications.

The Texas Instruments LMK04228 Ultra-Low-Noise Clock Jitter Cleaners combine high performance with features like the ability to trade-off between power or performance, dual VCOs, holdover, and per-output adjustable analog and digital delay. This makes the LMK04228 ideal for providing flexible, high-performance clocking trees.

Features

  • JEDEC JESD204B support
  • Ultra-low RMS jitter
    • 156fs RMS jitter (12kHz to 20MHz)
    • 245fs RMS jitter (100Hz to 20MHz)
    • –162.5dBc/Hz noise floor at 245.76MHz
  • Up to 14 differential device clocks from PLL2
    • Up to seven SYSREF clocks
    • Maximum clock output frequency of 1.25GHz
    • LVPECL, LVDS programmable outputs From PLL2
  • Buffered VCXO or crystal output from PLL1
    • LVPECL, LVDS, 2xLVCMOS programmable
  • Dual loop PLLatinum™ PLL architecture
  • PLL1
    • Up to three redundant input clocks
      • Automatic and manual switch-over modes
      • Hitless switching and LOS
    • Integrated low-noise crystal oscillator circuit
    • Holdover mode when input clocks are lost
  • PLL2
    • Normalized [1Hz] PLL noise floor of –224dBc/Hz
    • Phase detector rate up to 155MHz
    • OSC in frequency-doubler
    • Two integrated low-noise VCOs
  • 50% duty cycle output divides, 1 to 32 (even and odd)
  • Precision digital delay
  • 25ps step analog delay
  • Multi-mode: dual PLL or single PLL
  • -40°C to +85°C industrial temperature range 
  • 3.15V to 3.45V operation
  • 64-pin WQFN (9.0 × 9.0 × 0.8mm) package

Applications

  • Wireless infrastructure
  • Data converter clocking
  • Networking, SONET/SDH, DSLAM
  • Medical/video/military/aerospace
  • Test and measurement

Block Diagram

Block Diagram - Texas Instruments LMK04228 Ultra Low-Noise Clock Jitter Cleaners

Simplified Schematic

Schematic - Texas Instruments LMK04228 Ultra Low-Noise Clock Jitter Cleaners
Pubblicato: 2019-10-14 | Aggiornato: 2023-12-11