Texas Instruments Deserializzatore FPD-Link II DS90UR916Q-Q1
Il deserializzatore FPD-Link II DS90UR916Q di Texas Instruments funziona con il serializzatore DS90UR905Q per fornire dati video digitali a 24 bit su una singola coppia differenziale. Il deserializzatore TI DS90UR916Q offre funzionalità progettate per migliorare la qualità delle immagini sullo schermo. Il sistema bus seriale ad alta velocità di FPD-Link II semplifica notevolmente la progettazione del sistema, eliminando i problemi di allineamento tra clock e dati, riduce il numero di pin del connettore nonché la dimensione di interconnessione, il peso e il costo, e facilita il complessivo layout del PCB. Inoltre, la decodifica interna bilanciata CC serve per supportare interconnessioni di accoppiamento in CA. Il serializzatore DS90UR905Q incorpora l'orologio, bilancia il carico utile di dati e sposta il livello dei segnali sulla segnalazione differenziale a bassa tensione ad alta velocità.
The high speed serial bus scheme of FPD-Link II greatly eases system design by eliminating skew problems between clock and data, reduces the number of connector pins, reduces the interconnect size, weight, and cost, and overall eases PCB layout. In addition, internal DC balanced decoding is used to support AC-coupled interconnects. DS90UR905Q serializer embeds the clock, balances the data payload, and level shifts the signals to high-speed low voltage differential signaling.
The high speed serial bus scheme of FPD-Link II greatly eases system design by eliminating skew problems between clock and data, reduces the number of connector pins, reduces the interconnect size, weight, and cost, and overall eases PCB layout. In addition, internal DC balanced decoding is used to support AC-coupled interconnects. DS90UR905Q serializer embeds the clock, balances the data payload, and level shifts the signals to high-speed low voltage differential signaling.
Caratteristiche
- 5MHz-65MHz PCLK support (140Mbps-1.82Gbps)
- RGB888 + VS, HS, DE support
- Image enhancement - White balance LUTs and Adaptive Hi-FRC dithering
- AC coupled STP interconnect cable up to 10 meters
- @ Speed link BIST mode and reporting pin
- I2C compatible Serial Control Bus
- Power down mode minimizes power dissipation
- 1.8V or 3.3V compatible LVCMOS I/O interface
- Automotive grade product: AEC-Q100 Grade 2 qualified
- >8kV HBM and ISO 10605 ESD Rating
- FAST random data lock; no reference clock required
- Adjustable input receiver equalization
- LOCK (real time link status) reporting pin
- EMI minimization on output parallel bus (SSCG)
- Output Slew control (OS)
- Backward compatible mode for operation with older generation devices
Applicazioni
- Automotive displays
- Navigation
- Entertainment
Block Diagram
