Texas Instruments DACx0504 Voltage-Output DACs
Texas Instruments DACx0504 Voltage-Output Digital-to-Analog Converters (DACs) are low-power, four-channel, buffered voltage-output DACs with 16 or 14-bit resolution. The DACx0504 includes a low drift, 2.5- internal reference, eliminating the need for an external precision reference in most applications. A user-selectable gain configuration provides full-scale output voltages of 1.25V (gain = 1/2), 2.5V (gain = 1), or 5V (gain = 2). These devices operate from a single 2.7V to 5.5V supply, are specified monotonic, and provide high linearity of ±1LSB INL.Communication to the DACx0504 is performed through a 4-wire serial interface that operates at clock rates of up to 50MHz. The VIO pin enables serial interface operation from 1.7V to 5.5V. The DACx0504 flexible interface enables operation with a wide range of industry-standard microprocessors and microcontrollers.
The DACx0504 incorporates a power-on-reset circuit that powers up and maintains the DAC outputs at either zero scale or midscale until a valid code is written to the devices. These devices consume a low current of 0.7mA/channel at 5.5V, making them suitable for battery-operated equipment. A per-channel power-down feature reduces the current consumption to 15µA.
Features
- Performance
- INL: ±1LSB Maximum at 16-bit resolution
- TUE: ±0.1% of FSR Maximum
- Integrated 2.5 V precision internal reference
- Initial accuracy of ±5mV, maximum
- Low drift of 2ppm/°C typical, DAC80504
- High drive capability of 20mA with 0.5V from supply rails
- Flexible output configuration
- 2, 1 or 1/2 User selectable gain
- Reset to zero-scale or midscale
- Wide operating range
- 2.7V to 5.5V Power supply
- –40°C to +125°C Temperature
- 50MHz, SPI-Compatible serial interface
- 4-Wire Mode, 1.7V to 5.5V operation
- Daisy-chain operation
- CRC Error check
- Low power of 0.7mA/channel at 5.5V
- 3mm×3mm, 16-Pin WQFN Small package
Applications
- Optical networking
- Wireless infrastructure
- Industrial automation
- Data acquisition systems
Functional Block Diagram
Pubblicato: 2018-10-17
| Aggiornato: 2023-07-11
