Infineon Technologies S25FL512S FL-S NOR Flash Memory Devices
Infineon Technologies S25FL512S FL-S NOR Flash Memory Devices are VIO VCC 2.7V to 3.6V flash non-volatile memory devices. These devices use 65nm MirrorBit technology. Designed using Eclipse™ architecture with a 512-byte page programming buffer. The 512-Mb S25FL512S FL-S NOR allows users to program up to 256 words (512 bytes) in one operation. This results in faster effective programming and erase than prior generation SPI programs or erase algorithms. The device connects to a host system via an SPI and supports traditional SPI single-bit serial input and output. Optional two-bit (Dual I/O or DIO) and four-bit (Quad I/O or QIO) serial commands. The S25FL512S FL-S NOR provides support for Double Data Rate read commands for SIO, DIO, and QIO that transfer addresses.
The Infineon Technologies S25FL512S FL-S transfer address and read data on both edges of the clock. Using FL-S devices at the supported higher clock rates with QIO or DDR-QIO commands, the read transfer rate instruction can match traditional parallel interface, asynchronous, NOR flash memories while reducing signal count dramatically. S25FL512S FL-S NOR offers high-density performance capabilities coupled with the flexibility and speed required by various embedded applications. The S25FL512S FL-S NOR is ideal for code shadowing, XIP, and data storage.
Features
- CMOS 3.0 Volt Core with Versatile I/O
- Serial Peripheral Interface with Multi-I/O
- Density
- 512Mbits (64Mbytes)
- Serial Peripheral Interface (SPI)
- SPI clock polarity and phase modes 0 and 3
- Double Data Rate (DDR) option
- Extended addressing: 32-bit address
- Serial command set and footprint compatible with S25FL-A, S25FL-K, and S25FL-P SPI families
- Multi I/O command set and footprint compatible with S25FL-P SPI family
- READ Commands
- Normal, Fast, Dual, Quad, Fast DDR, Dual DDR, Quad DDR
- AutoBoot - power up or reset and execute a normal or quad read command automatically at a preselected address
- Common Flash Interface (CFI) data for configuration information
- Programming (1.5MB/s)
- 512-byte Page Programming buffer
- Quad-Input Page Programming (QPP) for slow clock systems
- Automatic ECC -internal hardware Error Correction Code generation with single bit error correction
- Erase (0.5 to 0.65MB/s)
- Uniform 256kbyte sectors
- Cycling Endurance
- 100,000 Program-Erase Cycles, minimum
- Data Retention
- 20-year data retention, minimum
- Security features
- One Time Program (OTP) array of 1024 bytes
- Block protection:
- Status register bits to control protection against program or erase of a contiguous range of sectors.
- Hardware and software control options
- Advanced Sector Protection (ASP)
- Individual sector protection is controlled by boot code or password
- Infineon® 65nm MirrorBit® Technology with Eclipse™ architecture
- Core supply voltage: 2.7V to 3.6V
- I/O supply voltage: 1.65V to 3.6V
- SO16 and FBGA packages
- Temperature range:
- Industrial (–40 °C to +85 °C)\Industrial Plus (–40 °C to +105 °C)
- Automotive, AEC-Q100 Grade 3 (–40 °C to +85 °C)
- Automotive, AEC-Q100 Grade 2 (–40 °C to +105 °C)
- Automotive, AEC-Q100 Grade 1 (–40 °C to +125 °C)
- Packages (all Pb-free)
- 16-lead SOIC (300mil)
- BGA-24 6 × 8mm
- 5 × 5 ball (FAB024) and 4 × 6 ball (FAC024) footprint options
- Known good die and known tested die
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